00001 /* -*- c++ -*- */ 00002 /* 00003 * Copyright 2004 Free Software Foundation, Inc. 00004 * 00005 * This file is part of GNU Radio 00006 * 00007 * GNU Radio is free software; you can redistribute it and/or modify 00008 * it under the terms of the GNU General Public License as published by 00009 * the Free Software Foundation; either version 3, or (at your option) 00010 * any later version. 00011 * 00012 * GNU Radio is distributed in the hope that it will be useful, 00013 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 * GNU General Public License for more details. 00016 * 00017 * You should have received a copy of the GNU General Public License 00018 * along with GNU Radio; see the file COPYING. If not, write to 00019 * the Free Software Foundation, Inc., 51 Franklin Street, 00020 * Boston, MA 02110-1301, USA. 00021 */ 00022 00023 #ifndef INCLUDED_AD9862_H 00024 #define INCLUDED_AD9862_H 00025 00026 /* 00027 * Analog Devices AD9862 registers and some fields 00028 */ 00029 00030 #define BEGIN_AD9862 namespace ad9862 { 00031 #define END_AD962 } 00032 #define DEF static const int 00033 00034 BEGIN_AD9862; 00035 00036 DEF REG_GENERAL = 0; 00037 DEF REG_RX_PWR_DN = 1; 00038 DEF RX_PWR_DN_VREF_DIFF = (1 << 7); 00039 DEF RX_PWR_DN_VREF = (1 << 6); 00040 DEF RX_PWR_DN_RX_DIGIGAL = (1 << 5); 00041 DEF RX_PWR_DN_RX_B = (1 << 4); 00042 DEF RX_PWR_DN_RX_A = (1 << 3); 00043 DEF RX_PWR_DN_BUF_B = (1 << 2); 00044 DEF RX_PWR_DN_BUF_A = (1 << 1); 00045 DEF RX_PWR_DN_ALL = (1 << 0); 00046 00047 DEF REG_RX_A = 2; // bypass input buffer / RxPGA 00048 DEF REG_RX_B = 3; // pypass input buffer / RxPGA 00049 DEF RX_X_BYPASS_INPUT_BUFFER = (1 << 7); 00050 00051 DEF REG_RX_MISC = 4; 00052 DEF RX_MISC_HS_DUTY_CYCLE = (1 << 2); 00053 DEF RX_MISC_SHARED_REF = (1 << 1); 00054 DEF RX_MISC_CLK_DUTY = (1 << 0); 00055 00056 DEF REG_RX_IF = 5; 00057 DEF RX_IF_THREE_STATE = (1 << 4); 00058 DEF RX_IF_USE_CLKOUT1 = (0 << 3); 00059 DEF RX_IF_USE_CLKOUT2 = (1 << 3); // aka Rx Retime 00060 DEF RX_IF_2S_COMP = (1 << 2); 00061 DEF RX_IF_INV_RX_SYNC = (1 << 1); 00062 DEF RX_IF_MUX_OUT = (1 << 0); 00063 00064 DEF REG_RX_DIGITAL = 6; 00065 DEF RX_DIGITAL_2_CHAN = (1 << 3); 00066 DEF RX_DIGITAL_KEEP_MINUS_VE = (1 << 2); 00067 DEF RX_DIGITAL_HILBERT = (1 << 1); 00068 DEF RX_DIGITAL_DECIMATE = (1 << 0); 00069 00070 DEF REG_RESERVED_7 = 7; 00071 00072 DEF REG_TX_PWR_DN = 8; 00073 DEF TX_PWR_DN_ALT_TIMING_MODE = (1 << 5); 00074 DEF TX_PWR_DN_TX_OFF_ENABLE = (1 << 4); 00075 DEF TX_PWR_DN_TX_DIGITAL = (1 << 3); 00076 DEF TX_PWR_DN_TX_ANALOG_B = 0x4; 00077 DEF TX_PWR_DN_TX_ANALOG_A = 0x2; 00078 DEF TX_PWR_DN_TX_ANALOG_BOTH = 0x7; 00079 00080 DEF REG_RESERVED_9 = 9; 00081 00082 DEF REG_TX_A_OFFSET_LO = 10; 00083 DEF REG_TX_A_OFFSET_HI = 11; 00084 DEF REG_TX_B_OFFSET_LO = 12; 00085 DEF REG_TX_B_OFFSET_HI = 13; 00086 00087 DEF REG_TX_A_GAIN = 14; // fine trim for matching 00088 DEF REG_TX_B_GAIN = 15; // fine trim for matching 00089 DEF TX_X_GAIN_COARSE_FULL = (3 << 6); 00090 DEF TX_X_GAIN_COARSE_1_HALF = (1 << 6); 00091 DEF TX_X_GAIN_COARSE_1_ELEVENTH = (0 << 6); 00092 00093 DEF REG_TX_PGA = 16; // 20 dB continuous gain in 0.1 dB steps 00094 // 0x00 = min gain (-20 dB) 00095 // 0xff = max gain ( 0 dB) 00096 00097 DEF REG_TX_MISC = 17; 00098 DEF TX_MISC_SLAVE_ENABLE = (1 << 1); 00099 DEF TX_MISC_TX_PGA_FAST = (1 << 0); 00100 00101 DEF REG_TX_IF = 18; 00102 DEF TX_IF_USE_CLKOUT2 = (0 << 6); 00103 DEF TX_IF_USE_CLKOUT1 = (1 << 6); // aka Tx Retime 00104 DEF TX_IF_I_FIRST = (0 << 5); 00105 DEF TX_IF_Q_FIRST = (1 << 5); 00106 DEF TX_IF_INV_TX_SYNC = (1 << 4); 00107 DEF TX_IF_2S_COMP = (1 << 3); 00108 DEF TX_IF_INVERSE_SAMPLE = (1 << 2); 00109 DEF TX_IF_TWO_EDGES = (1 << 1); 00110 DEF TX_IF_INTERLEAVED = (1 << 0); 00111 00112 DEF REG_TX_DIGITAL = 19; 00113 DEF TX_DIGITAL_2_DATA_PATHS = (1 << 4); 00114 DEF TX_DIGITAL_KEEP_NEGATIVE = (1 << 3); 00115 DEF TX_DIGITAL_HILBERT = (1 << 2); 00116 DEF TX_DIGITAL_INTERPOLATE_NONE = 0x0; 00117 DEF TX_DIGITAL_INTERPOLATE_2X = 0x1; 00118 DEF TX_DIGITAL_INTERPOLATE_4X = 0x2; 00119 00120 DEF REG_TX_MODULATOR = 20; 00121 DEF TX_MODULATOR_NEG_FINE_TUNE = (1 << 5); 00122 DEF TX_MODULATOR_DISABLE_NCO = (0 << 4); 00123 DEF TX_MODULATOR_ENABLE_NCO = (1 << 4); // aka Fine Mode 00124 DEF TX_MODULATOR_REAL_MIX_MODE = (1 << 3); 00125 DEF TX_MODULATOR_NEG_COARSE_TUNE = (1 << 2); 00126 DEF TX_MODULATOR_COARSE_MODULATION_NONE = 0x0; 00127 DEF TX_MODULATOR_COARSE_MODULATION_F_OVER_4 = 0x1; 00128 DEF TX_MODULATOR_COARSE_MODULATION_F_OVER_8 = 0x2; 00129 DEF TX_MODULATOR_CM_MASK = 0x7; 00130 00131 00132 DEF REG_TX_NCO_FTW_7_0 = 21; 00133 DEF REG_TX_NCO_FTW_15_8 = 22; 00134 DEF REG_TX_NCO_FTW_23_16= 23; 00135 00136 DEF REG_DLL = 24; 00137 DEF DLL_DISABLE_INTERNAL_XTAL_OSC = (1 << 6); // aka Input Clock Ctrl 00138 DEF DLL_ADC_DIV2 = (1 << 5); 00139 DEF DLL_MULT_1X = (0 << 3); 00140 DEF DLL_MULT_2X = (1 << 3); 00141 DEF DLL_MULT_4X = (2 << 3); 00142 DEF DLL_PWR_DN = (1 << 2); 00143 // undefined bit = (1 << 1); 00144 DEF DLL_FAST = (1 << 0); 00145 00146 DEF REG_CLKOUT = 25; 00147 DEF CLKOUT2_EQ_DLL = (0 << 6); 00148 DEF CLKOUT2_EQ_DLL_OVER_2 = (1 << 6); 00149 DEF CLKOUT2_EQ_DLL_OVER_4 = (2 << 6); 00150 DEF CLKOUT2_EQ_DLL_OVER_8 = (3 << 6); 00151 DEF CLKOUT_INVERT_CLKOUT2 = (1 << 5); 00152 DEF CLKOUT_DISABLE_CLKOUT2 = (1 << 4); 00153 // undefined bit = (1 << 3); 00154 // undefined bit = (1 << 2); 00155 DEF CLKOUT_INVERT_CLKOUT1 = (1 << 1); 00156 DEF CLKOUT_DISABLE_CLKOUT1 = (1 << 0); 00157 00158 DEF REG_AUX_ADC_A2_LO = 26; 00159 DEF REG_AUX_ADC_A2_HI = 27; 00160 DEF REG_AUX_ADC_A1_LO = 28; 00161 DEF REG_AUX_ADC_A1_HI = 29; 00162 DEF REG_AUX_ADC_B2_LO = 30; 00163 DEF REG_AUX_ADC_B2_HI = 31; 00164 DEF REG_AUX_ADC_B1_LO = 32; 00165 DEF REG_AUX_ADC_B1_HI = 33; 00166 00167 DEF REG_AUX_ADC_CTRL = 34; 00168 DEF AUX_ADC_CTRL_AUX_SPI = (1 << 7); 00169 DEF AUX_ADC_CTRL_SELBNOTA = (1 << 6); 00170 DEF AUX_ADC_CTRL_REFSEL_B = (1 << 5); 00171 DEF AUX_ADC_CTRL_SELECT_B2 = (0 << 4); 00172 DEF AUX_ADC_CTRL_SELECT_B1 = (1 << 4); 00173 DEF AUX_ADC_CTRL_START_B = (1 << 3); 00174 DEF AUX_ADC_CTRL_REFSEL_A = (1 << 2); 00175 DEF AUX_ADC_CTRL_SELECT_A2 = (0 << 1); 00176 DEF AUX_ADC_CTRL_SELECT_A1 = (1 << 1); 00177 DEF AUX_ADC_CTRL_START_A = (1 << 0); 00178 00179 DEF REG_AUX_ADC_CLK = 35; 00180 DEF AUX_ADC_CLK_CLK_OVER_4 = (1 << 0); 00181 00182 DEF REG_AUX_DAC_A = 36; 00183 DEF REG_AUX_DAC_B = 37; 00184 DEF REG_AUX_DAC_C = 38; 00185 00186 DEF REG_AUX_DAC_UPDATE = 39; 00187 DEF AUX_DAC_UPDATE_SLAVE_ENABLE = (1 << 7); 00188 DEF AUX_DAC_UPDATE_C = (1 << 2); 00189 DEF AUX_DAC_UPDATE_B = (1 << 1); 00190 DEF AUX_DAC_UPDATE_A = (1 << 0); 00191 00192 DEF REG_AUX_DAC_PWR_DN = 40; 00193 DEF AUX_DAC_PWR_DN_C = (1 << 2); 00194 DEF AUX_DAC_PWR_DN_B = (1 << 1); 00195 DEF AUX_DAC_PWR_DN_A = (1 << 0); 00196 00197 DEF REG_AUX_DAC_CTRL = 41; 00198 DEF AUX_DAC_CTRL_INV_C = (1 << 4); 00199 DEF AUX_DAC_CTRL_INV_B = (1 << 2); 00200 DEF AUX_DAC_CTRL_INV_A = (1 << 0); 00201 00202 DEF REG_SIGDELT_LO = 42; 00203 DEF REG_SIGDELT_HI = 43; 00204 00205 // 44 to 48 reserved 00206 00207 DEF REG_ADC_LOW_PWR_LO = 49; 00208 DEF REG_ADC_LOW_PWR_HI = 50; 00209 00210 // 51 to 62 reserved 00211 00212 DEF REG_CHIP_ID = 63; 00213 00214 00215 END_AD962; 00216 00217 #undef DEF 00218 #undef BEGIN_AD9862 00219 #undef END_AD962 00220 00221 #endif /* INCLUDED_AD9862_H */
1.6.3